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INTERNSHIP DETAILS

2026 Graduate - FPGA Engineering

CompanyQube Research & Technologies

LocationLondon

Work ModeOn Site

PostedJanuary 9, 2026

Internship Information

Core Responsibilities

As an intern or graduate in the FPGA team, you will contribute to the design, development, and optimization of custom FPGA-based trading platforms. You will work with SystemVerilog, C++, and Python to build, test, and refine high-performance, low-latency systems.

Internship Type

full time

Company Size

1977

Visa Sponsorship

Language

English

Working Hours

40 hours

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About The Company

Qube Research & Technologies (QRT) is a global quantitative and systematic investment manager, operating in all asset classes across the world. Driven by a shared passion for data, research, technology and trading expertise, we strive to deliver high-quality returns for our investors. Established in 2016, QRT can rely on its employees across 12 offices in Europe, Middle East and Asia Pacific. We currently have multiple open positions on our website, please check and apply on line: https://www.qube-rt.com/careers/ QRT supports various coding initiatives as well as academic projects developing and promoting maths and science education. More information: https://www.qube-rt.com/commitments

About the Role

Location: London    Programme duration: 3-6 months or 12-month industrial placement, or full-time graduate   Who qualifies: penultimate or final year students completing bachelor’s or master’s degree   Qube Research & Technologies (QRT) is a global quantitative and systematic investment manager, operating in all liquid asset classes across the world. We are a technology and data driven group implementing a scientific approach to investing. Combining data, research, technology, and trading expertise has shaped our collaborative mindset which enables us to solve the most complex challenges. QRT’s culture of innovation continuously drives our ambition to deliver high quality returns for our investors.    Over the years, QRT has invested in a global research and execution platform which has been deployed to cover all geographies and asset classes. This platform covers a broad spectrum from high to low frequency trading systems. We thrive at the intersection of cutting-edge technology, smart automation, and scalable processes, enabling us to move fast, think big, and deliver at scale.     We are committed to identifying and developing exceptional talent, and are inviting a new cohort of outstanding individuals to join us in the year ahead. Our internship offers a stimulating, intellectually rigorous, and high-performance environment, where collaboration is key to success. You will work alongside and be mentored by industry-leading professionals, gaining invaluable experience and positioning yourself for the opportunity to secure a full-time graduate role upon successful completion of the program.   Your future role at QRT  Throughout the recruitment process, we will work to align your skills, interests, and potential with the teams where you can make the greatest impact.    The FPGA (Field-Programmable Gate Array) team designs and builds ultra-low-latency hardware systems that power QRT’s trading platforms. By developing custom logic directly on cutting-edge FPGA devices, we enable trading strategies to process market data and execute orders with exceptional speed and precision. Working at the intersection of hardware and software, the team uses SystemVerilog, C++, and Python to deliver high-performance, reliable solutions that give QRT a competitive edge in global markets.  As an intern or graduate in the FPGA team, you will:  <ul> <li data-leveltext="" data-font="Symbol" data-listid="32" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Contribute to the design, development, and optimisation of custom FPGA-based trading platforms used in live trading. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="32" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Work with SystemVerilog, C++, and Python to build, test, and refine high-performance, low-latency systems. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="32" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Assist in implementing and verifying new FPGA features to improve market data processing and order execution speeds. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="32" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Collaborate with hardware and software engineers to integrate FPGA systems into QRT’s wider trading infrastructure. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="32" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Gain hands-on experience with state-of-the-art FPGA hardware and toolchains used in high-frequency trading. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="32" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Participate in performance analysis, debugging, and optimisation to ensure systems run with maximum efficiency. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="32" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Support ongoing research and development projects aimed at advancing FPGA capabilities as QRT grows. </li> </ul> Your current skillset   <ul> <li data-leveltext="" data-font="Symbol" data-listid="33" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Education – Penultimate or final year students working towards a Bachelor’s, Master’s, or PhD in Engineering, Information Technology, Computer Science, Electrical Engineering or a related field, on track to achieve a 2:1 or above from a leading institution.  </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="33" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Passion for Technology – Demonstrated interest in technology and engineering through achievements in software or hardware projects, whether academic, personal, or hobby-based — formal Computer Science training is not essential. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="33" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">  Technical Skills – </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="33" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="2">Experience or coursework in HDL (e.g., SystemVerilog, Verilog, or VHDL) </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="33" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="2">Programming skills in C++ and/or Python </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="33" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="2">Understanding of digital logic design, computer architecture, and high-speed interfaces </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="33" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="2">Familiarity with FPGA toolchains (e.g., Xilinx Vivado, Intel Quartus) is a plus </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="33" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Analytical & Problem-Solving Skills – Ability to troubleshoot and optimise designs for performance, resource usage, and power efficiency. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="33" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Mindset – Proactive, curious, and unafraid to ask questions, with the confidence to suggest and implement improvements that enhance performance. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="33" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Approach – Entrepreneurial, self-motivated, and results-driven. </li> </ul> Interviewing  <ul> <li data-leveltext="" data-font="Symbol" data-listid="15" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Apply Online - Applications are reviewed on a rolling basis, so we encourage you to apply early. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="15" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Technical Assessment - If your application is shortlisted, you’ll be invited to complete a coding challenge to assess your technical skills. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="15" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Shortlisting - Our engineering teams will review your background and coding challenge performance to select candidates for the next stage. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="15" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Interviews - Shortlisted candidates will receive requests to a range of technical and soft skill interviews via Teams or onsite. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="15" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Offer - Successful candidates will receive an offer to join QRT. </li> </ul> QRT is an equal opportunity employer. We welcome diversity as essential to our success. QRT empowers employees to work openly and respectfully to achieve collective success. In addition to professional achievement, we are offering initiatives and programs to enable employees achieve a healthy work-life balance.

Key Skills

FPGASystemVerilogC++PythonDigital Logic DesignComputer ArchitectureHigh-Speed InterfacesAnalytical SkillsProblem-Solving SkillsProactive MindsetCuriosityEntrepreneurial ApproachSelf-MotivatedResults-Driven