Design for Test Engineer Intern - CPU/AI Hardware

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>Be part of the team building the backbone of next-gen AI/ML chips. This role focuses on Design for Test (DFT) for high-performance IPs at the heart of industry-leading architectures. You'll work side-by-side with experienced engineers across the RTL, DFT, and Physical Design stack to bring silicon from idea to tapeout.</p> <p>This role is on-site, 40 hours, based out of Santa Clara, CA, Austin, TX or Ft Collins, CO.</p> <h3 data-start="591" data-end="610"><strong data-start="595" data-end="610">Who You Are</strong></h3> <ul> <li data-start="613" data-end="679">Curious about how complex chips are tested and verified at scale</li> <li data-start="613" data-end="679">Comfortable working with RTL and scripting languages like Tcl, Python, or Perl</li> <li data-start="613" data-end="679">Understand digital design basics, scan, and test techniques like ATPG or BIST</li> <li data-start="613" data-end="679">Actively pursuing a BS, MS, or PhD in EE, CE, ECE, or CS</li> </ul> <h3 data-start="912" data-end="932"><strong data-start="916" data-end="932">What We Need</strong></h3> <ul> <li>Help define and implement DFT architecture across various IPs</li> <li>Collaborate with cross-functional teams from RTL to physical design</li> <li data-start="1001" data-end="1070">Contribute to scan insertion, pattern generation, and verification workflows</li> <li data-start="1073" data-end="1151">Push test coverage higher using smart, automated solutions</li> </ul> <h3 data-start="1221" data-end="1248"><strong data-start="1225" data-end="1248">What You Will Learn</strong></h3> <ul> <li data-start="1251" data-end="1321">Full lifecycle of DFT—from RTL through pattern generation to tapeout</li> <li data-start="1251" data-end="1321">How real-world AI/ML chips are built and verified</li> <li data-start="1251" data-end="1321">Tools and flows used in cutting-edge ASIC development</li> <li data-start="1251" data-end="1321">How to debug, improve, and scale DFT infrastructure in complex SoCs</li> </ul> <div> <div> <p><em>Compensation for all interns at Tenstorrent ranges from $50/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.</em></p> <em>Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.</em></div> </div><div class="content-conclusion"><p><em>This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.</em></p></div>