Intern - DRAM Design Engineer

Contribute to the design, layout, and optimization of Memory/Logic/Analog circuits. Assist with parasitic modeling, design validation, reticle experiments, and tape-out revisions. Lead all aspects of layout processes including floor-planning, placement, and routing. Perform verification using industry-standard modeling and simulation tools. Collaborate with multi-functional teams to ensure manufacturability and build quality. Currently pursuing a Bachelor's, Master's, or PhD in Electrical or Computer Engineering, or equivalent experience. Must be continuing education in Fall 2024. Coursework or experience in circuit design, layout, or simulation. Familiarity with industry-standard EDA tools (e.g., Cadence, Synopsys). Strong communication and collaboration skills. Experience with parasitic modeling and tape-out processes. Exposure to semiconductor manufacturing or product integration. Hands-on experience with layout tools and verification methodologies. Prior internship or research in memory or logic circuit design. Understanding multi-functional collaboration within a semiconductor environment.