IP Design Verification - PEY

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>This Design Verification Intern role puts you at the heart of building the next generation of compute, not just watching from the sidelines. You’ll help push high‑speed digital and mixed‑signal blocks to their limits, write and run simulations that uncover real bugs, and see your work show up in decisions that ship real hardware. You’ll collaborate closely with experienced engineers, learn modern DV flows end‑to‑end, and leave with the kind of hands‑on impact most internships only talk about.</p> <p>&nbsp;</p> <p>Please note this is a 12-16 month internship.&nbsp;</p> <p>&nbsp;</p> <p>This role is<strong>&nbsp;</strong>hybrid based out of Toronto, Canada or Santa Clara, California office.&nbsp;</p> <p><strong>Who You Are</strong></p> <ul> <li>Senior-year undergrad or grad student in EE, CE, CS, or a related field.</li> <li>Comfortable with Verilog, SystemVerilog, or scripting languages.</li> <li>Familiar with computer architecture and interested in how chips really work.</li> <li>Analytical, curious, and ready to dive into the details of performance and functionality.</li> </ul> <p>&nbsp;</p> <p><strong>What We Need</strong></p> <ul> <li>Develop tests for functional and performance verification of chip inter-connection IP.</li> <li>Write and debug RTL, testbenches, and simulation environments.</li> <li>Support coverage, checkers, and verification infrastructure across subsystems.</li> <li>Help build tooling and workflows that scale across pre-silicon to post-silicon.</li> </ul> <p>&nbsp;</p> <p><strong>What You Will Learn</strong></p> <ul> <li>Industry-proven verification flows including simulation, emulation, and coverage.</li> <li>The full DV lifecycle: test planning, debug, execution, and closure.</li> <li>Collaboration with design, architecture, and performance teams in a real-world chip project.</li> <li>How AI is playing a significant role in the development of code, tools and flows.</li> </ul> <p>&nbsp;</p> <p><em>Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.</em></p><div class="content-conclusion"><p><em>This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.</em></p></div>