INTERNSHIP DETAILS

EOSL_EDA Design Intern (S100/S200)

CompanyITRI
LocationNot specified
Work ModeOn Site
PostedFebruary 5, 2026
Internship Information
Core Responsibilities
The intern will work on AI-driven EDA development and research, focusing on automated parameter exploration and optimization algorithms. They will also design and implement chip layout algorithms and develop numerical analysis and computational solvers.
Internship Type
full time
Company Size
5802
Visa Sponsorship
No
Language
English
Working Hours
40 hours
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About The Company
Industrial Technology Research Institute (ITRI)(工業技術研究院, 工研院) Industrial Technology Research Institute (ITRI) is one of the world's leading technology R&D institutions aiming to innovate a better future for society. Founded in 1973, ITRI has played a vital role in transforming Taiwan's industries from labor-intensive into technology-oriented. Over the years, ITRI has incubated over 240 innovative companies, including well-known names such as UMC and TSMC, and cultivated more than 140 CEOs. Based on its long-term partnership with various industry sectors, ITRI offers a wide range of services, from technical to business consultation, to the international community– such as contract research, product and process development, and pilot runs for technological upgrades; IP strategy and licensing, industrial analysis, and talent training for hi-tech business; and the open lab and incubation for new ventures and emerging industries. ITRI focuses on the fields of Information and Communications; Electronics and Optoelectronics; Material Chemical and Nanotechnology; Medical Device and Biomedical; Mechanical and Systems; and Green Energy and Environment. In addition to its headquarters in Taiwan, ITRI has branch offices in Silicon Valley, Tokyo, Berlin and Eindhoven in an effort to extend its R&D scope and promote opportunities for international cooperation around the world.
About the Role

This internship is in ITRI's Electronics and Optoelectronics Systems Research Laboratories (EOSL).

Intern will work on the following topics / tasks:

AI-Driven EDA Development and Research

  1. Develop fully automated parameter exploration and optimization algorithms and tools based on existing EDA platforms.
  2. Design and implement 2.5D/3D chip layout algorithms with considerations for power, performance, and area (PPA).
  3. Develop next-generation numerical analysis and computational solvers to accelerate convergence speed.
  4. Develop generative programming–based IP and SoC verification technologies to improve verification efficiency and convergence.


Qualifications:

  1. Major and student level: Master's or Ph.D. degree.
  2. Required/desired background with specific skills (software, equipment, processes, etc.): Educational or research background relevant to AI-driven EDA, chip layout optimization, numerical analysis, or SoC/IP verification.
  3. Language or other qualifications: Must be able to work on-site at the Hsinchu Zhongxing Campus.
Key Skills
AI-Driven EDAChip Layout OptimizationNumerical AnalysisSoC VerificationIP VerificationParameter ExplorationOptimization Algorithms3D Chip LayoutPower Performance AreaGenerative Programming
Categories
TechnologyEngineeringScience & Research