INTERNSHIP DETAILS

DFT Intern - ASIC Student - Israel - ETR

CompanyCisco
LocationKayseri
Work ModeOn Site
PostedMay 17, 2026
Internship Information
Core Responsibilities
The intern will be responsible for inserting Design for Test (DFT) logic, performing synthesis, and running Automatic Test Pattern Generation (ATPG) to ensure hardware testability. Core duties also include executing Gate Level Simulations, timing checks, and deep-dive debugging of simulation failures.
Internship Type
part time
Company Size
95451
Visa Sponsorship
No
Language
English
Working Hours
40 hours
Apply Now →

You'll be redirected to
the company's application page

About The Company
Cisco is the worldwide technology leader that is revolutionizing the way organizations connect and protect in the AI era. For more than 40 years, Cisco has securely connected the world. With its industry leading AI-powered solutions and services, Cisco enables its customers, partners and communities to unlock innovation, enhance productivity and strengthen digital resilience. With purpose at its core, Cisco remains committed to creating a more connected and inclusive future for all.
About the Role

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.

Who We Are

The Design for Test (DFT) team is part of the design group, which focuses on logic design, RTL development, and running verification tests. Their main role is to design test structures embedded within the chip to ensure proper functionality after manufacturing. The goal is to detect potential manufacturing defects with maximum efficiency and filter out faulty units before they reach the market.

The ideal candidate is friendly, social, easygoing, with a good sense of humor, and has the ability to learn independently. They should be located in central\north Israel (Tel-Aviv\Caesarea). Strong independent work skills and job stability are important. 

 

What You'll Do

Work in a small, agile team with an intimate atmosphere that offers direct mentoring and broad professional growth. Insert DFT logic, perform synthesis, and run Automatic Test Pattern Generation (ATPG) to ensure hardware testability. Execute Gate Level Simulations, timing checks, and DRC checks to maintain rigorous design integrity and performance standards. Run regressions and perform deep-dive debugging on simulation failures as part of the core verification process.

Minimum Qualifications

  • B.Sc or M.Sc Electrical/Computer Engineer student from leading Israeli Universities with average grades above 85.

  • Team players who enjoy big challenges.

  • People who can quickly ramp on multiple, interdisciplinary domains.

  • The position is suitable for students finishing their second or third year.

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

Key Skills
Design For TestLogic DesignRTL DevelopmentVerification TestsTest StructuresSynthesisATPGGate Level SimulationsTiming ChecksDRC ChecksDebuggingIndependent WorkTeamwork
Categories
EngineeringSoftwareScience & Research