INTERNSHIP DETAILS

ME Engineering Intern

CompanyAdvantest
LocationSan Jose
Work ModeOn Site
PostedMarch 13, 2026
Internship Information
Core Responsibilities
The intern will be responsible for executing complex test plans to quantify the performance of automated mating hardware, focusing on precision and repeatability. Key tasks include designing experiments to identify failure modes and analyzing performance data to define the system's Safe Operating Area.
Internship Type
full time
Company Size
3774
Visa Sponsorship
No
Language
English
Working Hours
40 hours
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About The Company
Advantest (TSE: 6857) is the leading manufacturer of automatic test and measurement equipment used in the design and production of semiconductors for applications including 5G communications, the Internet of Things (IoT), autonomous vehicles, high performance computing (HPC) including artificial intelligence (AI) and machine learning, and more. Its leading-edge systems and products are integrated into the most advanced semiconductor production lines in the world. The company also conducts R&D to address emerging testing challenges and applications; develops advanced test-interface solutions for wafer sort and final test; produces scanning electron microscopes essential to photomask manufacturing; and offers system-level test solutions and other test-related accessories. Founded in Tokyo in 1954, Advantest is a global company with facilities around the world and an international commitment to sustainable practices and social responsibility. More information is available at www.advantest.com.
About the Role

We are seeking a highly motivated Mechanical Engineering intern to assist in the development and validation of an automated high-precision mechanism designed to mate optical connectors to Silicon Photonic (SiPh) and Co-Packaged Optics (CPO) devices.In this role, you will bridge the gap between mechanical design and real-world performance. Your primary focus will be to test, evaluate, and characterize the automated system to identify its operational limits, ensuring sub-micron repeatability and long-term reliability in a high-stakes semiconductor testing environment.

  • Primary Responsibilities
  • System Characterization: Execute complex test plans to quantify the performance of automated mating hardware, focusing on precision, repeatability, and force profiles.
  • DOE & Limit Testing: Design and conduct Design of Experiments (DOE) to identify failure modes related to mechanical misalignment, thermal drift, and component wear.
  • Data-Driven Analysis: Collect and process mechanical and optical performance data to define the "Safe Operating Area" for the automation platform.
  • Hardware Iteration: Design and prototype custom jigs, fixtures, and end-of-arm tooling (EOAT) to improve alignment accuracy and connector protection.
  • Failure Mapping: Create a "Failure Catalog" documenting the mechanical and optical thresholds where the system performance degrades (e.g., insertion loss spikes or physical material wear).
Qualifications
  • Currently pursuing a BS or MS in Mechanical Engineering, Mechatronics, or a related field.
Key Skills
System CharacterizationDesign Of ExperimentsData AnalysisPrototypingFixture DesignTooling DesignMechanical DesignPrecision TestingRepeatability TestingFailure Analysis
Categories
EngineeringScience & ResearchManufacturingSoftware