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INTERNSHIP DETAILS

Layout Design Intern (Summer 2026)

CompanyCiena

LocationOttawa

Work ModeOn Site

PostedMay 1, 2026

Internship Information

Core Responsibilities

The intern will contribute to layout feasibility studies and develop custom layouts for advanced analog and mixed-signal blocks. They will also perform physical verification tasks such as DRC, LVS, and reliability analysis to ensure high-quality circuit designs.

Internship Type

full time

Salary Range

CA$25 - CA$34

Company Size

10357

Visa Sponsorship

Language

English

Working Hours

40 hours

Apply Now →

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About The Company

Ciena (NYSE:CIEN) is the global leader in high-speed connectivity. We build advanced networks to support exponential growth in bandwidth demand—empowering our customers, partners, and communities to thrive in the AI era. With unparalleled expertise and innovation, our networking systems, interconnects, automation software, and services revolutionize data transmission and network management.

About the Role

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

The WaveLogic™ family of products is a cornerstone of Ciena’s optical fiber transmission solutions and a key contributor to the company’s leadership in the global telecommunications industry. This opportunity offers hands‑on exposure to advanced high‑speed analog and mixed‑signal circuit design within a team that has shaped more than three decades of innovation in broadband fiber‑optic modems. The team pioneered the world’s first high‑speed digital‑to‑analog converter (DAC) and analog‑to‑digital converter (ADC) analog macros, enabling the evolution of coherent fiber‑optic product solutions.

This co‑op role provides the opportunity to contribute directly to next‑generation high‑speed circuit development while learning from experienced engineers in a collaborative, high‑performance environment.

How you will make an impact:

• Contribute to layout feasibility studies in partnership with senior analog designers, evaluating design trade‑offs and layout strategies for high‑speed circuits
• Develop custom layouts for advanced analog and mixed‑signal blocks, following structured methodologies for floorplanning, placement, and routing
• Execute comprehensive physical verification, including design rule checks (DRC), layout versus schematic (LVS), electromigration (EM), and infrared (IR) drop analysis to ensure layout quality and reliability
• Support continuous improvement by exploring new layout tool features, flows, and processes to enhance efficiency and productivity
• Collaborate closely with circuit designers and layout engineers to identify and resolve layout‑related risks early in the design cycle
• Provide clear status updates and actively participate in team meetings, design discussions, and knowledge‑sharing activities

The must haves:

• Currently pursuing a degree in Electrical Engineering or a related field
• Hands‑on experience with custom analog and mixed‑signal layout design in deep sub‑micron complementary metal‑oxide semiconductor (CMOS) technologies
• Strong understanding of layout techniques, including floorplanning, device matching, parasitic minimization, shielding, electromigration, and IR drop considerations
• Experience creating custom layouts for analog or mixed‑signal blocks such as operational amplifiers or current mirrors
• Familiarity with semiconductor manufacturing processes and foundry design rules
• Experience using industry‑standard layout tools such as Cadence Virtuoso and Siemens Calibre
• Ability to interpret and debug DRC and LVS reports effectively

Nice to haves:

• Exposure to high‑speed data converter or phase‑locked loop (PLL) layout design
• Familiarity with bipolar CMOS (BiCMOS) technologies
• Scripting experience using PERL or SKILL to support layout automation or productivity improvements
• Experience collaborating in cross‑functional hardware design teams
• Strong analytical skills with the ability to proactively identify layout‑sensitive circuit structures

Pay Range:

The hourly pay rate for this position is $25.00 – $34.00.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Key Skills

Analog circuit designMixed-signal circuit designLayout designFloorplanningPlacement and routingDRCLVSElectromigration analysisIR drop analysisCadence VirtuosoSiemens CalibreCMOS technologyDevice matchingParasitic minimizationShieldingSemiconductor manufacturing