Job Details:

Job Description:

Altera, provides industry-leading programmable solutions that are easy to use and deploy—from cloud applications to edge devices—enabling limitless AI possibilities. Our extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs, and IPUs, offering the flexibility necessary to accelerate innovation. We are part of the Digital IP group, dedicated to delivering next-generation IPs/ products to the market on time and with exceptional quality. 

About the Role: 

We are seeking a highly motivated intern currently holding a Master's degree in Electronics or Computer Engineering with a specialization in VLSI. The ideal candidate will possess foundational knowledge of VLSI design and verification, with additional experience in high-speed design challenges seen as advantageous. This ACE program provides an exciting opportunity to engage directly with verification activities for next-generation Altera FPGA products, specifically focusing on high-speed transceiver/ ethernet protocols.

Key Responsibilities: 

Support the FPGA verification team in ongoing and upcoming projects or new methodology initiatives. 

Assist in the development and implementation of innovative verification and debugging solutions. 

Document technical specifications clearly and maintain organized records of project progress. 

Collaborate closely with verification team members to understand and improve workflows and methodologies. 

Prepare and present updates and findings to stakeholders as required. 

Qualifications:

Skills and Qualifications: 

Familiarity with HDL languages (VHDL, Verilog, SystemVerilog). 

Experience or knowledge in scripting languages such as Tcl, Perl, or Python. 

Prior experience or exposure to FPGA tools (Quartus or Vivado) would be advantageous. 

Strong willingness to learn new skills and technologies. 

Ability to work collaboratively within a team environment. 

Good communication skills and ability to clearly present project details and outcomes.

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