INTERNSHIP DETAILS

Physical Design Intern

CompanyAmbiq Micro, Inc.
LocationSingapore
Work ModeOn Site
PostedSeptember 22, 2026
Internship Information
Core Responsibilities
The intern will support block-level physical implementation for SoC designs, including floorplanning, routing, and timing closure. They will also develop automation scripts and collaborate with cross-functional teams to resolve implementation issues.
Internship Type
full time
Company Size
234
Visa Sponsorship
No
Language
English
Working Hours
40 hours
Apply Now →

You'll be redirected to
the company's application page

About The Company
Ambiq® was founded in 2010 on the simple yet powerful notion that extremely low-power semiconductors are the key to the future of electronics. Through the use of pioneering ultra-low power technology, innovative companies around the world are developing differentiated solutions that reduce or eliminate the need for batteries, reduce overall system power and maximize industrial design flexibility. Our mission is to enable intelligence (artificial intelligence (AI) and beyond) everywhere by delivering the lowest power semiconductor solutions. We enable our customers to deliver artificial intelligence compute at the edge where power consumption challenges are the most profound. Our technology innovations, built on the patented and proprietary subthreshold power optimized technology (SPOT), fundamentally deliver a multi-fold improvement in power consumption over traditional semiconductor designs. We’ve powered over 270 million devices today. As we see the shift in devices move from “smart” to “AI,” our technology and solutions have evolved to accommodate the power requirements needed to enable feature rich devices that are always on, high performing, secure, accurate, energy efficient, and just as important practical. Our leadership in powering devices made for edge AI has helped technology innovators across wearable, smart home and buildings, industrial, healthcare, and other sectors deliver intelligent devices that can do more while consuming less. For more information, visit www.ambiq.com.
About the Role

Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.

 

Scope  

We’re looking for a Physical Design Intern to join our SoC team and help design, tape out ultra low power chips in advanced process nodes. In this role, you’ll gain hands-on experience with physical implementation tools, learn how to deliver best PPA designs, and work alongside experienced engineers to tape out ultra low power products. This internship is an excellent opportunity to apply what you’ve learned in class, explore industry-standard tools, and see how your work connects to the technology powering everyday devices. 

Responsibilities 

As a Physical Design Intern, you will:

  • Support block-level physical implementation for SoC designs
  • Assist with floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure
  • Run and analyze static timing analysis (STA) and help debug timing violations (setup/hold)
  • Help perform power, signal integrity, and IR drop analysis under guidance
  • Contribute to design rule check (DRC) and layout versus schematic (LVS) closure activities
  • Develop and maintain scripts (e.g., Tcl, Python, Shell) to automate recurring tasks
  • Document methods, results, and learnings; present progress to your mentor and team
  • Collaborate with RTL, verification, and physical design engineers to resolve implementation issues

Basic Qualifications 

  • Currently pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
  • Completed coursework in several of the following areas:
    • Digital logic design
    • VLSI design / physical design / ASIC design
    • CMOS circuits
    • Computer architecture (preferred)
  • Familiarity with Verilog or VHDL and digital design concepts (timing, pipelining, clocking)
  • Basic understanding of physical design concepts such as placement, routing, timing closure, clock trees, and power grid planning
  • Comfortable working in a Linux/UNIX environment
Key Skills
Physical designSoC designFloorplanningPlacementClock tree synthesisRoutingTiming closureStatic timing analysisDRCLVSTclPythonShellVerilogVHDLLinux
Categories
TechnologyEngineeringSoftware